x86asm.net2009-08-19T00:00:00Zx86asm.nethttp://x86asm.net/admin@x86asm.netx86asm.netfavicon.icox86asm.netX86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2010-01-20T00:00:00ZMostly a bugfix release.X86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2009-08-19T00:00:00ZAll SSE4, VMX and SMX instructions added, along with few
new general and system instructions. This makes the reference
up-to-date with current Intel processors.X86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2009-06-30T00:00:00ZBanzai! This is the first revision considered stable
(after more than two years of development). The overall structure
and many bugs have been fixed, no new instructions.UEFI Programming - First Stepsvidx86asm.net/articles/uefi-programming-first-steps2009-03-31T00:00:00Z2009-03-31T00:00:00ZIn this article, I will describe steps needed to start on with development of real UEFI
applications on x86 PC, and share some practical experiences with problems doing so.
I will focus on 64-bit version of UEFI, because the 32-bit version isn't much used
in this area (most likely due to Microsoft decision not to support UEFI in 32-bit Vista).
So, to follow some of my steps here, you'll need a 64-bit CPU (but not 64-bit OS, you
can use any 32-bit OS as well). We will finish this article with EFI Hello World application.X86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2008-12-17T00:00:00ZMostly a bugfix releaseIntroduction to UEFIvidx86asm.net/articles/introduction-to-uefi2008-07-31T00:00:00Z2008-10-24T00:00:00ZNew revision: Added Mark Larson's reaction; few minor fixesX86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2008-10-19T00:00:00ZNew revision, massive update to the reference: All SSE, SSE2, SSE3, and SSSE3 instructions
added; alphabetically sorted editions; the store improved, prices
discountedUEFI Hypervisors - Winning the Race to Bare MetalDon Baileyx86asm.net/articles/uefi-hypervisors-winning-the-race-to-bare-metal2008-09-24T00:00:00Z2008-09-24T00:00:00ZImprovements in Operating Systems security have created a race to
"bare metal" between malware and protection software authors. Bare
metal capabilities are defined as software or firmware applications
that run outside the context of the OS and are therefore very powerful
and difficult to detect. Hypervisors and SMM based rootkits are
examples of bare metal capabilities. Because the digital battle
ground is contracting, advantage goes to the one who can establish
a presence there first.Introduction to UEFIvidx86asm.net/articles/introduction-to-uefi2008-07-31T00:00:00Z2008-07-31T00:00:00ZIn the beginning, there was BIOS (I assume reader knows what BIOS is). Back in those times, processors were
running in 16-bit mode, and RAM was architecturally limited to 1 megabyte. As the evolution went forth,
came 32-bit, and later 64-bit x86 CPUs, amount of RAM was increasing, and new ways of accessing it were being
developed. But BIOS remained same. This situation was was far from ideal, since BIOS code was very limited,
and operating system loader had to load kernel just with using the most basic BIOS services, from 20 years ago.
Creating new standard seemed impossible on such diverse market. But it was done anyway. X86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2008-05-15T00:00:00ZNew Revision: All MMX instructions added; benefits for contributorsPortable x86 Flat SyntaxMazeGenx86asm.net/articles/portable-x86-flat-syntax2008-04-18T00:00:00Z2008-04-18T00:00:00ZFrom time to time, speculations about portable
assembler (what is a contradiction itself) araise. As an assembly
programmer, I couldn't avoid these weird speculations. The
similarity between x86-32 and x64 simply can't be overlooked and
itself leads to finding some conjunctive syntax, here called Portable
x86 Flat Syntax (PFS).X86 Opcode and Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2008-03-11T00:00:00ZNew Revision: All x87 FPU instructions added, including
new ones; The l column was renamed to x and now holds more
information; In HTML a PDF editions, the prefix values were moved
to pf column; On-line store opened; The project was renamed to X86 Opcode and Instruction ReferenceOOP From Low-level Perspectivevidx86asm.net/articles/oop-from-low-level-perspective2008-02-06T00:00:00Z2008-02-06T00:00:00ZFor many lowlevel programmers, object oriented programming (OOP) tends to be
confusing and filled with abstractions. In this article I build up and explain
some aspects of OOP from C or Assembly programmer's point of view.Fixed Point Arithmetic and TricksGabriel Ivancescux86asm.net/articles/assemblers/fixed-point-arithmetic-and-tricks2007-12-21T00:00:00Z2007-12-21T00:00:00ZI see many people get confused at fixed point and believe
it's some kind of "hack" because they think floating point are
"real" numbers. Real numbers are abstract mathematical
representation - computers are not abstract, they do not employ
normal mathematics (for example, infinite numbers). It only tries
to "emulate" the abstract math (bits being volts, holes, magnetic
charges, etc). People who use floating point to represent
fractional parts definitely don't know what float is.FASMLIB 0.8.0vidhttp://fasmlib.x86asm.net/download.html2007-03-04T00:00:00Z2007-12-06T00:00:00ZWhat's new: qword conversion added, HTML documentation
added, several changes / fixes / improvements
x86 Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2007-11-29T00:00:00ZNew Revision: The HTML table is split into two parts: one-byte and
two-byte opcode part. This should make browsers to render
it faster and more easily. I hope this also helps Firefox
to render the table at first (without refresh);
Instructions, which doesn't really test all flags but
push them on the stack (PUSHF, INT and few others) are
corrected (suggested by Wolfgang Kern);
PDF edition for each HTML editionCalling BIOS from Driver in Windows XP x64vidx86asm.net/articles/assemblers/calling-bios-from-driver-in-windows-xp-x642007-11-26T00:00:00Z2007-11-26T00:00:00ZAs we all know, we shouldn't call BIOS from Windows
drivers, and Windows officially doesn't support this. But
recently, I was in situation where I had to do it, so I looked for
some way how.Using SSE Registers for General Purpose. SIMD with General-purpose RegistersMadis Kalmex86asm.net/articles/assemblers/using-xmm-for-general-purpose-simd-with-gpr2007-11-26T00:00:00Z2007-11-26T00:00:00ZNowadays the goal of a new CPU is not to give you the
highest clock rates, not even the highest performance (while it's
still a big part of it), but to give you the best
performance-per-watt number. While specific instructions are
introduced, the course is to perform best in every possible
application. May it be for office work, scientific, educational or
gaming.Working with Big Numbers Using x86 Instructionsvidx86asm.net/articles/assemblers/working-with-big-numbers-using-x86-instructions2007-11-20T00:00:00Z2007-11-20T00:00:00ZNew revision: Partial rewrite and additionsFDBG 001A finalFerynofdbg.x86asm.net/download.html2007-03-20T00:00:00Z2007-11-12T00:00:00Zfinished fdbg version 001A for win64x86 Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2007-11-06T00:00:00ZNew revision: Added coder, coder32, coder64, geek32, and
geek64 editions. All main project's files modified. Project's
documentation completed.Working with Big Numbers Using x86 Instructionsvidx86asm.net/articles/assemblers/working-with-big-numbers-using-x86-instructions2007-11-06T00:00:00Z2007-11-06T00:00:00Z"Big number" arithmetics requires special care on x86
architecture. You need to use some properties of arithmetic
instructions, which are not immediately apparent.Backdoor Support for Control-Transfer Breakpoint Features in Windows x64Ferynox86asm.net/articles/backdoor-support-for-control-transfer-breakpoint-features2007-09-31T00:00:00Z2007-09-31T00:00:00ZIt is well known that both AMD64 and Intel EM64T CPUs
support Control-Transfer Breakpoint Features. When I was trying to
implement this feature in FDBG, a hidden backdoor was discovered,
which makes the implementation very easy.FDBG 001A betaFerynofdbg.x86asm.net/download.html2007-03-20T00:00:00Z2007-10-30T00:00:00Zn/aFASMLIB 0.7.0vidfasmlib.x86asm.net/download.html2007-03-04T00:00:00Z2007-10-23T00:00:00ZThis is after long time first "stable" release version.x86-64 Tour of Intel ManualsMazeGenx86asm.net/articles/x86-64-tour-of-intel-manuals2007-10-04T00:00:00Z2007-10-04T00:00:00ZI'm always surprised by how few asmers use probably the
best source of information available - official processor
manuals, either Intel's or AMD's. That's why this article was
written. It should guide you step by step through complexity of
Intel manuals, describing x86-64 architecture in the
process.Debugging in AMD64 64-bit Mode in TheoryFerynox86asm.net/articles/debugging-in-amd64-64-bit-mode-in-theory2007-09-29T00:00:00Z2007-09-29T00:00:00ZA debugger is kind of blackbox for a regular user. The
interactions between debugger and OS are kept under the
cover. Let's uncover them and see how it all works.What I Dislike About GASvidx86asm.net/articles/assemblers/what-i-dislike-about-gas2007-09-28T00:00:00Z2007-09-28T00:00:00ZI often get to argument with various linux guys about
AT&T versus Intel syntax. There are many things I dislike on AT&T
syntax, so I decided to write them all down in this
article.Memory Allocation in Linuxvidx86asm.net/articles/memory-allocation-in-linux2007-09-24T00:00:00Z2007-09-24T00:00:00ZMany assembly programmers make linux applications using
only syscalls, without glibc. Altough this way is usually
considered bad practice, it is a fact.External Dependencies in Assemblersvidx86asm.net/articles/assemblers/external-dependencies-in-assemblers2007-08-15T00:00:00Z2007-08-15T00:00:00ZEach assembler handles external dependencies on its
own. I have investigated various assemblers and made interesting
discussion.x86 Instruction ReferenceMazeGenref.x86asm.net2007-06-04T00:00:00Z2007-06-04T00:00:00ZThis reference should be precise instruction set
reference (including x86-64). Its principal aim is exact
definition of instruction parameters and attributes.